phase detector/frequency synthesizer adf4002-ep rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features 400 mhz bandwidth 2.7 v to 3.3 v power supply separate charge pump supply (v p ) allows extended tuning voltage in 3 v systems programmable charge pump currents 3-wire serial interface analog and digital lock detect hardware and software power-down mode 104 mhz phase frequency detector supports defense and aerospace applications (aqec standard) military temperature range: ?55c to +125c controlled manufacturing baseline one assembly/test site one fabrication site enhanced product change notification qualification data available on request applications clock conditioning clock generation if lo generation general description the adf4002-ep frequency synthesizer is used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. it consists of a low noise digital phase frequency detector (pfd), a precision charge pump, a programmable reference divider, and a programmable n divider. the 14-bit reference counter (r counter) allows selectable ref in frequencies at the pfd input. a complete phase-locked loop (pll) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (vco). in addition, by programming r and n to 1, the part can be used as a stand- alone pfd and charge pump. additional application and technical information can be found in the adf4002 data sheet. functional block diagram clk data le ref in rf in a rf in b 24-bit input register sd out a v dd dv dd ce agnd dgnd 14-bit r counter r counter latch 22 14 function latch n counter latch 13-bit n counter m3 m2 m1 mux sd out av dd high-z muxout cpgnd r set v p cp phase frequency detector lock detect reference charge pump current setting 1 adf4002-ep cpi3 cpi2 cpi1 cpi6 cpi5 cpi4 current setting 2 09187-001 figure 1.
adf4002-ep rev. 0 | page 2 of 8 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing characteristics ................................................................ 4 absolute maximum ratings ............................................................5 ? thermal characteristics ...............................................................5 ? esd caution...................................................................................5 ? pin configuration and function descriptions ..............................6 ? typical performance characteristics ..............................................7 ? outline dimensions ..........................................................................8 ? ordering guide .............................................................................8 ? revision history 11 /10revision 0: initial version
adf4002-ep rev. 0 | page 3 of 8 specifications av dd = dv dd = 3 v 10%, av dd v p 5.5 v, agnd = dgnd = cpgnd = 0 v, r set = 5.1 k, dbm referred to 50 , t a = t max to t min , unless otherwise noted. operating temperature range is ?55c to +125c. table 1. parameter min typ max unit test conditions/comments rf characteristics rf input sensitivity ?10 0 dbm rf input frequency (rf in ) 5 400 mhz for rf in < 5 mhz, ensure slew rate (sr) > 4 v/s ref in characteristics ref in input frequency 20 300 mhz for ref in < 20 mhz, ensure sr > 50 v/s ref in input sensitivity 1 0.8 av dd v p-p biased at av dd /2 (ac coupling ensures av dd /2 bias) ref in input capacitance 10 pf ref in input current 100 a phase frequency detector (pfd) phase detector frequency 2 104 mhz abp[2:1] = 00 (2.9 ns antibacklash pulse width) charge pump programmable i cp sink/source high value 5 ma r set = 5.1 k low value 625 a absolute accuracy 2.5 % r set = 5.1 k r set range 3.0 11 k i cp three-state leakage 1 na t a = 25c i cp vs. v cp 1.5 % 0.5 v v cp (v p ? 0.5 v) sink and source current matching 2 % 0.5 v v cp (v p ? 0.5 v) i cp vs. temperature 2 % v cp = v p /2 logic inputs input high voltage, v ih 1.4 v input low voltage, v il 0.6 v input current, i inh , i inl 1 a input capacitance, c in 10 pf logic outputs output high voltage, v oh 1.4 v open-drain output, 1 k pull-up resistor to 1.8 v dv dd ? 0.4 v cmos output output high current, i oh 100 a output low voltage, v ol 0.4 v i ol = 500 a power supplies av dd 2.7 3.3 v dv dd av dd v v p av dd 5.5 v av dd v p 5.5 v i dd 3 (ai dd + di dd ) 5.0 6.0 ma i p 0.4 ma t a = 25c power-down mode 1 a ai dd + di dd noise characteristics normalized phase noise floor (pn synth ) 4 , 5 ?222 dbc/hz pll loop bandwidth = 500 khz normalized 1/f noise (pn 1_f ) 4 , 6 ?119 dbc/hz measured at 10 khz offset; normalized to 1 ghz 1 av dd = dv dd = 3 v. 2 guaranteed by design. sample tested to ensure compliance. 3 t a = 25c; av dd = dv dd = 3 v; rf in = 350 mhz. the current for any other setup (25 c, 3.0 v) in ma is given by 2.35 + 0.0046 (ref in ) + 0.0062 (rf); rf frequency and ref in frequency in mhz. 4 all phase noise measureme nts were performed with a rohde & schwarz fsup26 phas e noise test system us ing the eval-adf4002ebz1 e valuation board and the ultralow noise, 100 mhz ocxo from wenzel (part no. 501-16843) as the pll reference. 5 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 2 0logn (where n is the n divider value) and 10logf pfd . pn synth = pn tot ? 10logf pfd ? 20logn. 6 the pll phase noise is composed of 1/f (flicker) noise plus the normalized pll noise floor. the formula for calculating the 1/ f noise contribution at an rf frequency (f rf ) and at a frequency offset (f) is given by pn = p 1_f + 10log(10 khz/f) + 20log(f rf /1 ghz). both the normalized phase noise floor and the flicker noise ar e modeled in adisimpll.
adf4002-ep rev. 0 | page 4 of 8 timing characteristics av dd = dv dd = 3 v 10%, av dd v p 5.5 v, agnd = dgnd = cpgnd = 0 v, r set = 5.1 k, dbm referred to 50 , t a = t max to t min , unless otherwise noted. operating temperature range is ?55c to +125c. table 2. parameter limit 1 unit description t 1 10 ns min data to clk setup time t 2 10 ns min data to clk hold time t 3 25 ns min clk high duration t 4 25 ns min clk low duration t 5 10 ns min clk to le setup time t 6 20 ns min le pulse width 1 guaranteed by design, but not production tested. timing diagram clk db22 db2 data le t 1 le db23 (msb) t 2 db1 (control bit c2) db0 (lsb) (control bit c1) t 3 t 4 t 6 t 5 09187-022 figure 2. timing diagram
adf4002-ep rev. 0 | page 5 of 8 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd 1 ?0.3 v to +3.6 v av dd to dv dd ?0.3 v to +0.3 v v p to gnd 1 ?0.3 v to +5.8 v v p to av dd ?0.3 v to +5.8 v digital i/o voltage to gnd 1 ?0.3 v to dv dd + 0.3 v analog i/o voltage to gnd 1 ?0.3 v to v p + 0.3 v ref in , rf in a, rf in b to gnd 1 ?0.3 v to av dd + 0.3 v operating temperature range industrial ?55c to +125c storage temperature range ?65c to +125c maximum junction temperature 150c lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c transistor count cmos 6425 bipolar 303 1 gnd = agnd = dgnd = cpgnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. thermal characteristics table 4. thermal impedance package type ja unit tssop (ru-16) 150.4 c/w esd caution
adf4002-ep rev. 0 | page 6 of 8 pin configuration and fu nction descriptions r set cp cpgnd agnd muxout le data clk ce dgnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 rf in b rf in a av dd ref in v p dv dd adf4002-ep top view (not to scale) pin 1 indicator 09187-002 figure 3. pin configuration (top view) table 5. pin function descriptions pin no. mnemonic description 1 r set connecting a resistor between this pin and cpgnd se ts the maximum charge pump output current. the nominal voltage potential at the r set pin is 0.66 v. the relationship between i cp and r set is set maxcp r i 25.5 = where r set = 5.1 k and i cp max = 5 ma. 2 cp charge pump output. when enabled, this output provides i cp to the external loop filter that, in turn, drives the external vco. 3 cpgnd charge pump ground. this is the ground return path for the charge pump. 4 agnd analog ground. this is the ground return path of the rf input. 5 rf in b complementary input to the rf input. this pin must be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. 6 rf in a input to the rf input. this small-signal input is ac-coupled to the external vco. 7 av dd analog power supply. this can range from 2.7 v to 3.3 v. decoupling capacitors to the analog ground plane should be placed as close as possible to the av dd pin. av dd must be the same value as dv dd . 8 ref in reference input. this cmos input has a nominal threshold of av dd /2 and a dc equivalent input resistance of 100 k. this input can be driven from a ttl or cmos crystal oscillator or it can be ac-coupled. 9 dgnd digital ground. 10 ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three- state mode. taking this pin high powers up the device, depending on the status of the power-down bit pd1. 11 clk serial clock input. the serial clock is used to clock in th e serial data to the registers. the data is latched into the 24-bit shift register on the clk rising edge . this input is a high impedance cmos input. 12 data serial data input. the serial data is loaded msb first; the two lsbs are the control bits. this input is a high impedance cmos input. 13 le load enable. when le goes high, the da ta stored in the shift registers is loaded into one of the four latches; the latch is selected using the control bits. this input is a high impedance cmos input. 14 muxout multiplexer output. this output allows the lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. 15 dv dd digital power supply. this can range from 2.7 v to 3.3 v. decoupling capacitors to the digital ground plane should be placed as close as possible to the dv dd pin. dv dd must be the same value as av dd . 16 v p charge pump power supply. this should be greater than or equal to av dd . in systems where av dd is 3 v, v p can be set to 5.5 v and used to drive a vco with a tuning voltage of up to 5 v.
adf4002-ep rev. 0 | page 7 of 8 typical performance characteristics 09187-031 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 100 200 300 400 500 600 power (dbm) frequency (mhz) +25c +125c ?55c figure 4. rf input sensitivity ?35 ?30 ?25 ?20 ? 15 5 7 9 11 13 15 power (dbm) frequency (mhz) +25c +125c ?55c 09187-033 figure 5. rf input sensitivity, low frequency ? 70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency offset (hz) rms noise = 0.07 degrees 09187-031 figure 6. integrated phase noise (400 mhz, 1 mhz, 50 khz) ? 130 ?135 ?140 ?145 ?155 ?160 ?165 ?170 ?175 ?180 100k 1m 10m 100m 1g phase noise (dbc/hz) pfd frequency (hz) ?150 09187-033 figure 7. phase noise (referred to cp output) vs. pfd frequency ref ?4dbm samp log 10db/ attn 10db vbw 20khz mkr1 1.000 mhz ?94.5dbc center 399.995mhz res bw 20khz span 2.2mhz sweep 21ms (601pts) ?94.5dbc 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?90 ?100 ?80 1 1r 09187-030 figure 8. reference spurs (400 mhz, 1 mhz, 7 khz)
adf4002-ep rev. 0 | page 8 of 8 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 9. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model temperature range packag e description package option adf4002sru-ep ?55c to +125c 16-lead tssop ru-16 ADF4002SRU-EP-RL7 ?55c to +125c 16-lead tssop ru-16 ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09187-0-11 /10(0)
|
